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| T5552 Read/Write IDIC Micromodule with 1 Kbit Memory Description The T5552 is a two terminal, contactless R/W-IDentification IC (IDIC)* for tag applications in the 125 kHz ( 25 kHz) range. The IC uses the external RF signal to generate it's own power supply and internal clock reference. It is built into a standard micromodule wich is suitable for contactless R/W identification applications. It is a plastic encapsulated package on a copper lead-frame substate. The micromodule contains the IDIC with a total of 1056 bits of EEPROM memory grouped into 32 individually addressable data blocks and a 435-pF capacitor. Each block of the IDIC is made up of 32 bits of data plus an associated lock bit for block write protection. Blocks 1 to 31 are provided for user related data and block 0 for system configuration. Data is transmitted from the IC (uplink) using reflective load (backscatter) modulation. This is achieved by damping the external RF field by switching a resistive load between the two terminals Clock-A/Clock-B as shown in figure 14 (downlink). The IC receives and decodes amplitude modulated data from the base station. As soon as the tag included the T5552 is exposed to an RF field and the field is strong enough to derive enough energy to operate, the tag will respond by continuously transmitting stored data (uplink mode). The base station can at any time switch the tag into downlink mode to write new user or configuration data. Generally the tag will automatically return to the default uplink mode when the downlink transfer is complete or interrupted or if an error condition occurs. Features D Low power, low voltage operation D Contactless power supply D Contactless read/write data transmission D Radio Frequency (RF): 100 kHz to 150 kHz D 1056 bits of EEPROM memory D 992 bits (31 x 32 bits) of user memory D Defined start of data transmission D Auto-verify after EEPROM programming D 400 mm thickness of the micromodule D 435-pF capacitor D Block write protection for each block D Configurable options include: - Modulation type: - Bit rate [bit/s]: - Max block feature - Modulation defeat - POR start-up delay: PSK | Manchester RF/16 | RF/32 1 ms | 65 ms Applications D Industrial asset management D Process control and automation D Logistic process flow monitoring Transponder Micromodule Coil interface Power Base station Data downlink Data uplink Coil 2 Coil 1 Controller C Figure 1. Transponder system example using T5552 * IDIC stands for IDentification Integrated Circuit and is a trademark of Atmel Wireless & Microcontrollers Rev. A1, 04-May-01 Memory 1 (12) T5552 Ordering Information Extended Type Number T555200 - PAE Package Micromodule Remarks Reel; 35 mm; 3 rows; 435 pF Functional Modules Analog Front End (AFE) The analog front end (AFE) includes all circuits which are directly connected to the coil. It generates the IC's power supply and handles the bidirectional data communication with the basestation. It consists of the following blocks: D Rectifier to generate a DC supply voltage from the AC coil voltage. D ESD protection D Clock extractor D Switchable load between Coil 1/ Coil 2 for data transmission from the IC to the reader electronics (uplink mode). D Field gap detector for data transmission from the base station to the IC (downlink mode). Data Rate Generator The data rate in uplink mode can be selected to operate at either RF/16 (nominally 7.81 kHz, default) or RF/32 (nominally 3.91 kHz). Bit Decoder This function block decodes the field gaps and verifies the validity of the incoming data stream. Charge Pump This circuit generates the high voltage required for programming the EEPROM. Power-On Reset (POR) This circuit delays the IC's functionality until an acceptable voltage threshold has been reached. Controller The control logic is responsible for the following: D Initializing and refresh configuration register from EEPROM block 0. D Controlling read and write memory accesses. D Handling data transmission and opcode decoding. D Error detection and error handling. Mode Register This register holds the configuration data bits stored in EEPROM block 0. It is refreshed at the start of every block read operation. Modulator The modulator encodes the serial data stream shifted out of the selected EEPROM data block and controls the damping circuit in the AFE. The T5552 frontend supports PSK and Manchester encoding. Clock Extraction The clock extraction circuit generates the internal clock source out of the external RF signal. 2 (12) Rev. A1, 04-May-01 T5552 Analog front end (rectifier, regulator, clock extractor, ESD protection) POR Coil 1 Bit rate generator Bit decoder Modulator Coil 2 16543 16547 Input register Charge pump Start-up delay Controller Mode register EEPROM memory Figure 2. Functional block diagram Operating the T5552 Damping on Damping off Loading block 0 (114 FC [ 1 ms), start-up delay inactive Read data with selected modulation and bitrate Power-on reset Figure 3. Voltage at Coil 1/ Coil 2 after power on General The basic functions of the T5552 are to supply the IC from the RF field, read data out of the EEPROM and shift them to the modulator, receive data and program these data bits into the EEPROM. An error detecting circuit prevents the EEPROM from being written with wrong data. Initialization The occurrence of a RF field triggers a power-on reset pulse, ensuring a defined start-up. The Power-On-Reset circuit (POR) remains active until an adequate voltage threshold has been reached. This in turn triggers the default start-up delay sequence. During this period of 114 field clock cycles (FC) the T5552 is initialized with the configuration data stored in EEPROM block 0. This is followed by an additional delay time which is defined by the "Start-up Delay" bit. If the "Start-up Delay" bit is set the T5552 remains inactive until 8192 RF clock cycles have occured. If this option is deactivated, no delay is observed after the configuration period of 114 RF clock cycles ( 1 ms). Power Supply The IC is supplied via a tuned LC circuit which is connected to the Coil 1/Coil 2 pads. The incoming RF induces a current in the coil. The on-chip rectifier generates the DC supply voltage. Overvoltage protection prevents the IC from damage due to high field strengths. Depending on the coil, the open-circuit voltage across the LC circuit can reach more than 100 V. Rev. A1, 04-May-01 3 (12) T5552 MAXBLK = 0 Loading block 0 MAXBLK = 1 0 Block 1 Block 1 Block 1 Block 1 Block 1 Block 1 Block 1 .... Loading block 0 .... MAXBLK = 2 Loading block 0 MAXBLK = 31 Loading block 0 (not transmitted) Any field gap occuring during initialization will restart the complete sequence. T INIT = (114 + 8,192*delay bit)/125 kHz 65 ms After this initialization time the T5552 enters uplink mode and modulation starts automatically using the parameters defined in the configuration block. Uplink Operation All transmissions from the IC to the base station utilizes amplitude modulation (ASK) of the RF carrier. This takes place by switching a resistive load between the coil pads (Coil 1 and Coil 2) which in turn modulates the RF field generated by the base station (reflective backscatter modulation). MaxBlock Data from the memory is serially transmitted, starting with block 1, bit 1, up to the last block (MAXBLK), bit 32. The last block which will be transmitted is defined by the mode parameter field MAXBLK is stored in EEPROM block 0. When the MAXBLK address has been reached, data transmission restarts with block 1. The user defines the cyclic datastream by setting the MAXBLK between 0 and 31 (representing each of the 32 4 (12) II II II II II 0 0 Block 0 Block 0 Block 0 Block 0 Block 0 Block 0 Block 0 .... Block 1 Block 2 Block 1 Block 2 Block 1 Block 2 Block 1 II II 0 Block 1 Block 2 Block 30 Block 31 Block 1 Block 2 .... 16546 Refreshing configuration register Figure 4. Datastream pattern depending on MAXBLK data blocks). If set to 1, only block 1 is transmitted. If set to 31, blocks 1 to 31 will be sequentially transmitted. If set to 0, only the contents of the configuration block (normally not accessible) will be transmitted (see figure 4). On the other hand it is also possible to access a single data block selectively, independant of the MAXBLK value, with the direct access command (Opcode `11'). The thus addressed data block is transmitted repeatedly. Data Encoding Everytime when entering uplink mode, the data stream is preceeded by a single start bit (always `0'). Then the data stream continues with block 1, bit 1, and continues through MAXBLK, bit 32. This data stream pattern cycles continuously. The modulator is configurable for D MANCHESTER Manchester encoded data represent a logical `1' with a rising edge and a logical `0' with a falling edge. D PSK using sub-carrier frequency RF/2 The PSK modulator changes phase with each change of data. The first phase shift represents a data change from `0' --> `1'. Rev. A1, 04-May-01 T5552 1 Data rate = 16 Field Clocks (FC) 8 FC Datastream Manchester encoded 9 12 RF-field 8 16 1 8 9 16 1 8 16 1 8 9 16 8 FC 0 0 1 16552 Figure 5. Example of Manchester encoding with data rate RF/16 1 Data rate = 16 Field Clocks (FC) 8 FC Datastream Inverted modulator signal subcarrier RF/2 12 89 161 8 FC 0 0 1 8 16 1 8 16 1 8 RF-field 16559 Figure 6. Example of PSK encoding with data rate RF/16 Downlink Operation Data is transmitted from the base station by amplitude modulation of the field (m = 1) using a series of so called gaps. With the exception of the initial synchronisation gap (start gap), all field gaps have the same duration, the logical data being encoded in the length of the unmodulated phases (see figure 7) Rev. A1, 04-May-01 A valid data stream is always preceeded by a start gap which is approximately twice as long as a normal field gap. Detection of this first gap causes the T5552 to switch immediately into the downlink mode where it can receive and decode the following data stream. This stream consists of two opcode bits, followed by (0, 3 or 5) address bits and finally (0 or 33) data bits (including the lock bit). In downlink mode the transponder damping is perma5 (12) T5552 nently enabled. This loads the resonant transponder coil circuit so that it comes quickly to rest when field gaps occur - thus allowing fast gap detection. Read mode RF Damping ON Damping OFF Field gap + data '0` Field gap + data '1` Start gap + data '0` 16548 Downlink Data Coding The duration of a field gap is typically between 80 and 250 s. After the start gap the data bits are transmitted by the base station whereby each bit is separated by a field gap. The bit decoder interprets 16 to 32 internal field clocks as a logical `0' and 48 to 64 internal field clocks as a logical `1' (see figure 8). Therefore the time between two gaps is typically 24 field clocks for a `0' and 56 field clocks for a `1'. Whenever the bit decoder detects more than 64 field clocks, the T5552 will abort the downlink mode. The incoming data stream is checked continuously and should an error be detected the corresponding error handling is initiated. The control logic initiates an EEPROM programming cycle if the correct number of bits had been received (see figure 9). Receive mode Figure 7. Entering the downlink mode A start gap will be accepted at any time after start-up initialization has been finished (RF field ON plus 1 ms, startup delay inactive) and the IC is not in downlink operation. Uplink mode Data stream check start gap detected ? YES NO YES OPCODE '11' ? NO NO Downlink mode count field clocks FC OPCODE '10 ' ? YES Execute command '00' or '01' FC count > 64 ? NO gap detected ? YES YES Data stream check YES YES bitcount = 38 ? NO NO bitcount = 40 ? NO Programming YES 16 <= FC <= 32 ? NO YES '0' into shift register NO bitcount = 7 ? YES enter error handler -> "Frame error" '1' into shift register enter uplink mode ->block 1...MAXBLK 48 <= FC <= 64 ? NO enter error handler -> "Bit Error" Uplink mode Direct access mode enter uplink mode -> selected block 16550 16552 Figure 8. Operation of bit decoder - data stream decoder Figure 9. Data stream checking 6 (12) Rev. A1, 04-May-01 T5552 Standard block write Short block write Direct access command Reset command OP 11 L 1 OP 10 L 1 OP 11 4 OP 10 Figure 10. T5552 opcode format definition Addr Data bits Data bits 0 16560 32 4 32 2 Addr 0 Addr 0 Opcode definitions The first two bits of the data stream are decoded by the controller as the opcode bits (see figure 10): `11': Opcode for a 5-bit address data stream D To initiate a standard block write cycle the 2 opcode bits are followed by the lock bit, the 32 data bits and the 5-bit block address (40 bits total). D The direct access command consists of the opcode `11' followed by the 5-bit block address and is a read- only command (7 bits total). `10': Opcode for a 3-bit address data stream D e5550 receive mode compatible To initiate a block write cycle, the opcode `10' is followed by the lock bit, the 32 data bits and the 3-bit block address (38 bits total). `01': reserved for production test commands. PROGRAMMING turn off transponder damping addressed block locked ? NO YES generate high programming voltage erase block NO erase successful ? YES `00': Opcode for an internal reset command. program '1's NO programming '1's successful ? YES enter error handler -> "Verification error" enter uplink mode -> read selected block enter "Modulation Defeat" 16551 Figure 11. Programming cycle flow chart Rev. A1, 04-May-01 7 (12) T5552 Programming If the bit decoder and controller detect a valid data stream, the T5552 will start an erase and programming cycle if a data write command was decoded (see figure 11). During the erase and programming cycle downlink damping is turned off. The programming cycle includes a data verification read to check the integrity of the data. After EEPROM programming and verification has been finished successfully, the T5552 enters uplink mode transmitting the block just programmed. The typical programming time is 18 ms. EEPROM Memory Organisation The memory array of the T5552 consists of 1,056 bits of EEPROM, arranged in 32 individually addressable blocks of 33 bits each, consisting of one lock bit and 32 data bits. All 33 bits, including the lock bit, are programmed simultaneously. The programming voltage is generated on-chip. Lock bit Each block has an associated write lock bit with which the entire block can be protected. By default all lock bits L are reset (`0'). Note: Once set, the lock bit - and the content of the associated block - cannot be altered. Error Handling Several error conditions are detected by the T5552 to ensure that only valid information is programmed into the EEPROM. Memory Map The configuration data of the T5552 is stored in block 0 of the EEPROM. The remaining thirty-one data blocks (1 .. 31) each consist of one lock bit and 32 user data bits. 01 L L L Configuration data block User data bits User data bits 32 Block 0 Block 1 Block 2 Errors During EEPROM Programming There are two error types which will lead to different actions. D Verification error If one of the data verification cycles fails, the T5552 will inhibit modulation and not return to the uplink mode. This "modulation defeat" state is terminated by re-entering the downlink mode with a start gap. D Block write protection If the lock bit of the addressed block is set, programming is disabled. In this case, the programming cycle is not initiated and the T5552 reverts to uplink mode, transmitting the currently addressed (and unmodified) block continuously. L L L User data bits User data bits User data bits Block 29 Block 30 Block 31 33 bits total (incl. one lock bit) Not transmitted Figure 12. Memory map 16549 Errors During Data Transmission The following errors are detected by the decoder: D Bit error Wrong number of field clocks between two gaps (i.e. not a valid `0' or `1' pulse stream). D Frame error The number of data bits received is incorrect: - valid bit count for 3-bit address write is 38 bits - valid bit count for 5-bit address write is 40 bits or - 7 bits for a direct access command. If any of these conditions is detected, the T5552 enters uplink mode starting with block 1. 8 (12) Configuration Data Block This data block contains 9 configuration bits. The remaining bits of block 0 are reserved for future enhancements and should be set to `0'. D Start-up Delay bit (SD, default: NO delay) When set, an additional delay time of 64 ms is added after any internal reset. D Data Rate bit (DR, default: RF/16) Selects data rate of RF/16 or RF/32. D Modulation Select bit (MS, default is PSK) Selects type of data encoding which is either MANCHESTER or PSK. D Modulation Defeat bit (MD, default is OFF) When set (to `1') the modulation output is deactiRev. A1, 04-May-01 T5552 vated, hence no data will be transmitted. The "modulation defeat" state does not impact the transponder damping function. D MAXBLK address This 5-bit block address is used to define the upper limit of cyclic block reads. Note: The configuration is changed by re-programming block 0 as long as the corresponding lock bit is not set. T5552 Configuration Block 0 L 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 000000000 0 0 0 0 0 0 0 0 0 0 0 0 0 Start-up delay SD Data rate DR Modul. select MS 0 reserved, to be '0` Lockbit MAXBLOCK MD Modulation Defeat 0 = Normal function 1 = Modulation off 0 = Unlocked 1 = Locked NO delay = 0 Delay of 8,192 field clocks = 1 Figure 13. T5552 configuration block 0 bit mapping 0 = PSK 1 = MANCHESTER 0 = RF/16 1 = RF/32 Rev. A1, 04-May-01 9 (12) reserved T5552 Absolute Maximum Ratings Parameters Maximum DC current into Coil 1/ Coil 2 Maximum AC current into Coil 1/ Coil 2, f = 125 kHz Power dissipation (dice) 1) 2) Symbol Icoil Icoil PP Ptot Tamb Tstg Value 10 20 100 -25 to +75 -40 to +125 Unit mA mA mW C C Operation ambient temperature range Storage temperature range Notes: 1) Free-air condition, time of application: 1s 2) Data retention reduced Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Operating Charateristics Tamb = 25C; fRF = 125 kHz reference terminal is VSS Parameters RF frequency range Supply current Uplink & downlink mode - full temperature range Programming - full temperature range Clamp voltage Programming time Startup time Data retention Programming cycles Coil 1/ 2 voltage Coil 1/ 2 voltage Damping resistor Capacitance value Capacitance Q Capacitance temperature coefficient 500 mV / 125 kHz 10 mA current into ClockA/B Per block 2) 1) 1) Uplink & downlink mode Programming, RF field w/o damping Each at Clock-A and Clock-B Test Conditions / Pins Symbol fRF IDD IDD Vclamp tP t startup t retention ncycles VclockPP VclockPP RD C Q DC 1 20 100,000 6 12 1.5 435 300 68 ppm/K V V k pF 7 18 65 Min. 100 Typ. 125 5 14 Max. 150 7.5 28 11 Unit kHz A A V ms ms Years Note: 1) Since EEPROM performance is influenced by assembly and packaging, TEMIC Semiconductors confirm the parameters for DOW (= tested dice on wafer) and ICs assembled in standard package. 2) Depends on start-up delay bit in configuration register 10 (12) Rev. A1, 04-May-01 T5552 Micromodule Dimensions in mm Lead Frame Specification Pitch Module size Mold dimension Lead frame Bond pad size Surface plating Module thickness 9.5 mm 5 8 mm 5.1 4.9 mm CuSn6 100 m 5 1.5 mm 2.5 m Ag 400 m maximum Temperature Profile for Processing 150_C / 5 min 390_C / 3 s 500_C / 25 ms Rev. A1, 04-May-01 11 (12) T5552 Ozone Depleting Substances Policy Statement It is the policy of Atmel Germany GmbH to 1. Meet all present and future national and international statutory requirements. 2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances (ODSs). The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances. Atmel Germany GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents. 1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively 2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental Protection Agency (EPA) in the USA 3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively. Atmel Germany GmbH can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances. We reserve the right to make changes to improve technical design and may do so without further notice. Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use Atmel Wireless & Microcontrollers products for any unintended or unauthorized application, the buyer shall indemnify Atmel Wireless & Microcontrollers against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. Data sheets can also be retrieved from the Internet: http://www.atmel-wm.com Atmel Germany GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany Telephone: 49 (0)7131 67 2594, Fax number: 49 (0)7131 67 2423 12 (12) Rev. A1, 04-May-01 |
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